module mulcycle_fsqrt
#(
    parameter val_width=52,
    parameter out_width=val_width/2,
    step_wid=$clog2(val_width)
)
(
    input [val_width-1:0]op_a,
    input datavalid,
    input clk,rst,
    output reg ready,
    output reg [out_width-1:0]sqrt_o
);
	parameter IDLE = 2'd0;
	parameter CALC = 2'd1;
	parameter DONE = 2'd3;
	reg [val_width:0]mid;
	reg [1:0]state;
	reg [step_wid-1:0]SCNT;
	reg [1:0]next_state;
	always @(posedge clk or negedge rst_n)
	begin
		if(!rst_n)state<=0;
		else state=next_state;
	end
	always @(*)
	begin
		case(state)
		default:
		begin
			if(start)
				next_state=CALC;
			else next_state=IDLE;
		end
		CALC:
		begin
			if(SCNT==(div_width/2-1))next_state=DONE;
			else next_state=CALC;
		end
		DONE:
		begin
			next_state=IDLE;
		end
		endcase
		
	end
	reg [val_width+1:0]remainder;
    reg [out_width-1:0]quotient;
    
	always @(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
		begin
			//DIV<=0;
            ready<=1;
            sqrt_o<=0;
            quotient<=0;
		end
		else
			case(next_state)
			default://IDLE
			begin
				remainder<=op_a;
				SCNT<=0;
				ready<=1;
			end
			CALC:
			begin
				ready<=0;
				SCNT<=SCNT+1;
                if(remainder[val_width])  //if 2*R(N-1)<0
                begin
                    quotient[out_width-SCNT-1]=0;
                    remainder <= remainder<<1+();
                end
                else 
                begin                       //remainder>0
                    quotient[out_width-SCNT-1]=1;
                    remainder <= remainder<<1-();
                end
			end
			DONE:
			begin
				ready<=1;
			end
			endcase
		
	end
endmodule